Metis Insight #1

MetisX is proud to launch Metis Insight, our publication series dedicated to introducing our core technologies and exploring new trends in the field of memory-centric computing. In our inaugural publication, we delve into the intricate concept of cache coherency.

Are you familiar with the concept of Cache Coherency, a key feature of the CXL Protocol? Cache coherency is a technology that ensures the data stored in the caches of multiple processors or accelerators remains consistent when they access the same memory data.

Let's consider a simple example: imagine a system where both the CPU and GPU handle the same memory data. When these processors reference the same memory address and process data, each stores the data in its own cache memory for rapid processing. If the CPU modifies this data, the change is reflected only in the CPU’s cache, while the GPU’s cache still contains the old data. If the GPU retrieves and processes this data, it uses outdated information, leading to conflicts. To prevent such issues, the system may need to employ protocols that ensure cache coherency. Typically, the MESI protocol is used. MESI is an acronym for Modified, Exclusive, Shared, Invalid, which represent four exclusive states of cache lines..

CXL Computational Memory, which features built-in computational capabilities, also requires cache coherency as conflicts may arise during processing with the host’s cache data. How then does CXL Computational Memory ensure cache coherency? The CXL3.0 spec supports a Back-invalidate Snoop within the CXL.mem Sub-protocol, allowing devices to directly manage the state of caches used by the host.

The Back-invalidation Snoop operates as follows:
1) Metadata Storage: The host’s cache state information is recorded in the device’s Snoop Filter.
2) State Monitoring and Comparison: If a specific cache line’s data is modified by the host or device, it is compared with the metadata stored in the Snoop Filter.
3) Back-Invalidation: If the changes do not match the metadata, an Invalidation Signal is sent to the host's cache to invalidate the cached data, thus maintaining cache coherency.

By supporting the CXL3.0 Spec, MetisX’s CXL Computational Memory enhances cache coherency, reducing unnecessary data movement and enabling efficient big data processing.